Conception et réalisation d'oscillateurs accordables en fréquence en technologie SiGe pour les radio-téléphones

LIMOGES-BU Sciences (870852109) / SudocSudocFranceF

Application des technologies CMOS sur SOI aux fonctions d'interface des liens de communication haut débit (>10Gbit/s)

L'objectif de ce travail est d'étudier les avantages de la technologie CMOS/SOI 0.13 m partiellement désertée, pour la conception des circuits d'interface des liens haut débit (10 et 40gbit/s). Nous avons identifié une fonction critique : la récupération de l'horloge et des données (CDR). L'étude de cette fonction nous a conduit à une analyse approfondie de l'oscillateur commande en tension (VCO). Neuf circuits VCO et oscillateurs 10ghz ont ainsi été conçus pour valider les choix technologiques offerts par le CMOS/SOI. Les performances mesurées démontrent l'intérêt du CMOS/SOI pour les applications à hautes fréquences. Pour les applications à 40gbit/s, nous avons ensuite conçu, réalisé et testé un VCO multi-phases 4x10ghz. Les résultats expérimentaux montrent une amélioration significative de la figure de mérite lorsque l'on compare ce circuit en CMOS/SOI avec les résultats précédemment publiés.GRENOBLE1-BU Sciences (384212103) / SudocSudocFranceF

Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop

International audienc

Built-in test of millimeter-wave circuits based on non-intrusive sensors

International audienc

Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors

International audienceTesting the RF functions of systems-on-chip incurs a very high cost. Built-in test is a promising alternative to facilitate testing and reduce cost. However, designing built-in test circuits that tap into the sensitive RF signal paths, in order to extract useful information for the purpose of testing, often finds the designers reluctant since it results in some performance degradation that needs to be accounted for during the design. In this paper, we study a transparent built-in test approach based on non-intrusive sensors that are not electrically connected to the RF circuit under test. The non-intrusive sensors simply monitor process variations and by virtue of this they are capable of tracking variations in the performances of the RF circuit as well. The alternate test paradigm is employed to map the outputs of the sensors to the performances, in order to replace the standard tests for measuring the performances directly. We discuss in this paper the principle of operation of these sensors and we demonstrate the non-intrusive test approach on a 65nm RF low noise amplifier

Conception et réalisation d'oscillateurs contrôlés en tension en Silicium Germanium pour les radiocommunications sans fil

National audienc

Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology

International audienceThis paper deals with the design of a fractional PLL for wireless multi-standard applications. This circuit has been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. Five standards are covered by this structure: GSM (900 MHz), DCS (1.8 GHz), Bluetooth (2.45 GHz) and 802.11a (5.8 GHz). Based on multi-engine simulators, associated with a hierarchical models library, a virtual RF system platform, which allows designing complex SoCs, is also presented. The PLL, including digital and analogue parts, constitutes a very good benchmark to validate this platform

Ultralow-phase-noise oscillators based on BAW resonators

This paper presents two 2.1-GHz low-phase noise oscillators based on BAW resonators. Both a single-ended common base structure and a differential Colpitts structure have been implemented in a 0.25-μm BiCMOS process. The detailed design methods including the realization, optimization, and test are reported. The differential Colpitts structure exhibits a phase noise 6.5 dB lower than the single-ended structure because of its good performance of power noise immunity. Comparison between the two structures is also carried out. The differential Colpitts structure shows a phase noise level of −87 dBc/Hz at 1-kHz offset frequency and a phase noise floor of −162 dBc/Hz, with an output power close to −6.5 dBm and a core consumption of 21.6 mW. Furthermore, with the proposed optimization methods, both proposed devices have achieved promising phase noise performance compared with state-of-the-art oscillators described in the literature. Finally, we briefly present the application of the proposed BAW oscillator to a micro-atomic clock